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Bart Plackle shared thisChiplets for the win indeed ! Tenstorrent has been an awesome AECP partner from the first hour ! Great technology Great team !Bart Plackle shared this𝗝𝗶𝗺 𝗞𝗲𝗹𝗹𝗲𝗿 𝗷𝘂𝘀𝘁 𝘀𝗮𝗶𝗱 𝗧𝗲𝗻𝘀𝘁𝗼𝗿𝗿𝗲𝗻𝘁 𝘄𝗶𝗹𝗹 "𝗯𝗲𝗮𝘁 𝗖𝗲𝗿𝗲𝗯𝗿𝗮𝘀 𝗼𝗻 𝗲𝘃𝗲𝗿𝘆𝘁𝗵𝗶𝗻𝗴." That is a clear statement from someone who does not trade in empty claims. In a recent interview with EE Times, Keller confirmed he has been meeting with Intel and Qualcomm CEOs, saying he is "hoping to get a big deal" out of one of them. He also said Cerebras going public was helpful, specifically in the context of Tenstorrent positioning to beat them. Whether Tenstorrent gets acquired or goes public itself, the company is in the spotlight now. Jim has a tremendous track record — AMD K8, Apple A4/A5, Tesla's FSD chip. He builds architectures that ship. Tenstorrent is building chiplet-based AI processors designed for disaggregated compute. The approach splits inference and training workloads across multiple smaller dies instead of one massive monolithic chip. That matters for cost, yield, and thermal management in production environments. Keller has been public about the limitations of current GPU-centric infrastructure. His pitch is that chiplets give you flexibility at scale without the packaging constraints that come with wafer-scale designs. Cerebras proved the concept. Tenstorrent is positioning to make it commercially viable. Bloomberg reported in May that Tenstorrent has held early-stage takeover conversations with both Intel and Qualcomm. A partnership or acquisition would give either company a credible alternative architecture to work with. Industry analysts have framed Tenstorrent as the only credible RISC-V AI platform on the market that is not building from scratch. The question is not whether chiplet-based AI accelerators are real. The question is whether Tenstorrent can ship at volume before the hyperscalers lock in their next-generation infrastructure plans. Click here to subscribe to The Hirsch Report: https://lnkd.in/gyzanhxn Source Article: https://lnkd.in/gd8ApZGG #AI #Semiconductors #Tenstorrent #Cerebras #Intel #Qualcomm #Chiplets #HirschReport
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Bart Plackle shared thisWho am I to disagree with our big bos 🤷♂️ trust me in saying that the journey only just got started 🙏🙏 Kudos to Michael Windig and the team on what they already accomplished in just one year, one word : impressive!Bart Plackle shared thisOne thing became very clear during my visit to Germany this week: as AI increasingly moves beyond datacenters into cars, factories, robots and critical infrastructure, Europe has an opportunity to build on its strengths in industrial systems, advanced manufacturing and energy-efficient computing. Edge AI, Physical AI and chiplet-based architectures are areas where Europe can compete differently. These themes were at the heart of a breakfast roundtable in Berlin, where we exchanged views with policymakers, industry leaders and research partners on Germany, Flanders/Belgium and Europe's semiconductor challenges. Through imec Germany in Heilbronn, we are committed to supporting the German ecosystem and strengthening collaboration between Germany, Flanders, Baden-Württemberg and the broader European ecosystem. Together with Jo De Boeck and Minister-President Matthias Diependaele, we continued these discussions in Dresden at Silicon Saxony Days, where we engaged with the broader ecosystem, visited ESMC, and highlighted the role of imec's NanoIC pilot line in bridging research and industrial deployment. This also reinforces our conviction that specialized, application-driven architectures will be key to Europe's competitiveness, a philosophy reflected in initiatives such as imec's Autonomous Edge Chiplet Program (AECP). 👉 https://lnkd.in/emrJy4dw The key now is execution.
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Bart Plackle shared thisAnother good read on why we are doing what we are doing 🤷♂️Bart Plackle shared this𝗘𝘅𝗽𝗲𝗿𝘁 𝗽𝗲𝗿𝘀𝗽𝗲𝗰𝘁𝗶𝘃𝗲 🔹When does it make sense to move from a monolithic #ASIC to a #chiplet-based design? By Christopher Hunat & Nidhish Gaur - imec https://lnkd.in/emuFQPte A journey into the benefits, trade-offs and technical implications of moving to chiplets Read more at https://lnkd.in/emuFQPte #chiplet #3DIC #AdvancedPackaging #MultiDie #semiconductor
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Bart Plackle shared thisGood read on chiplets , the reality is spreading 💪💪
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Bart Plackle shared this#Proud , today at Global Semiconductor Alliance executive forum our CEO Patrick Vandenameele announced our first chiplet reference platform for autonomous edge, a platform we are jointly building with NXP Semiconductors Axelera AI and Valeo ! “The best way to predict the future is to invent it” —Alan Kay
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Bart Plackle shared thisIf you want to help rebuild europe semi industry , time is now , place is here !Bart Plackle shared thisAs advanced packaging becomes a critical ingredient in the autonomous edge and AI/HPC era, testing complex multi-chiplet packages and systems will be crucial at the same time. From the implementation of required DFT mechanisms and cross-chiplet scan chains (IEEE1149 / IEEE1838), wafer- & package-level tests including state-of-the art ATE, all the way up to system-level validation including a mix of established standards (AEC-Q104) and novel approaches (e.g., mission-profile based robustness validation), this is a great opportunity to join the imec Germany team in Heilbronn! 🚀
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Bart Plackle shared thisThat's a wrap to our 7th , now called Autonomous Edge chiplet Forum (AECF). A very big thanks to all the awesome partners who spend 2 half days at imec to get the chiplet state of the union on what is happening in the land of auto(nomous), Great partners/friends networking & collectively setting future direction BIG THANK YOU ALL ,and see you in Tokyo Fall 2026!! Let us know in he comments how it went ?
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Bart Plackle shared thisWith the start of our 7th (auto)nomous chiplet forum at imec Leuven it’s time to finally let the cat out the bag 🙀 The whole team proudly presents the “Autonomous Edge Chiplet Program “ AECP and “Autonomous Edge Chiplet forum” AECF Full rational and details in the article below Hope to see many of you tomorrow 🙏🙏Bart Plackle shared thisFrom autonomous vehicles to robotics, industrial automation, aerospace, and security systems, the demand for edge AI compute is accelerating. Meeting that demand will require more than incremental chip scaling. It calls for new ways to design, integrate, and optimize increasingly complex systems. That is why imec is broadening its Automotive Chiplet Program into the 𝗔𝘂𝘁𝗼𝗻𝗼𝗺𝗼𝘂𝘀 𝗘𝗱𝗴𝗲 𝗖𝗵𝗶𝗽𝗹𝗲𝘁 𝗣𝗿𝗼𝗴𝗿𝗮𝗺 (𝗔𝗘𝗖𝗣). Building on the strong foundation of automotive innovation, AECP expands its focus to support a 𝗯𝗿𝗼𝗮𝗱𝗲𝗿 𝗲𝗰𝗼𝘀𝘆𝘀𝘁𝗲𝗺 𝗱𝗲𝘃𝗲𝗹𝗼𝗽𝗶𝗻𝗴 𝗻𝗲𝘅𝘁-𝗴𝗲𝗻𝗲𝗿𝗮𝘁𝗶𝗼𝗻 𝗮𝘂𝘁𝗼𝗻𝗼𝗺𝗼𝘂𝘀 𝗲𝗱𝗴𝗲 𝘀𝘆𝘀𝘁𝗲𝗺𝘀. By bringing together partners across the value chain, the program aims to accelerate chiplet-based architectures that deliver the performance, efficiency, safety, and scalability these applications require. Curious about what this evolution means for the future of edge HPC? And how can a shared chiplet foundation accelerate innovation across domains? 𝗥𝗲𝗮𝗱 𝘁𝗵𝗲 𝗮𝗿𝘁𝗶𝗰𝗹𝗲 and discover how chiplets are helping shape the next generation of autonomous systems 👉 https://lnkd.in/dg9AVTYn.
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Bart Plackle shared thisGood read if you want to understand why #imec is focusing on chiplets and why this is the right strategy for Europe 🙏💪Bart Plackle shared thisTowards an open chiplet ecosystem...Chiplets and Europe’s Post-Fab Semiconductor Strategy - EE TimesChiplets and Europe’s Post-Fab Semiconductor Strategy - EE Times
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Bart Plackle liked thisBart Plackle liked this🔊 Next up… a voice you won’t want to miss at the TechWorks S2S26 Summit, please welcome Robert Moran, SVP & GM Automotive Processors, NXP Semiconductors. Robert will be talking about how as AI expands beyond the cloud and into physical systems, a new architectural paradigm is emerging: the Neural Axis. Inspired by the human nervous system, this approach distributes intelligence across three coordinated layers—reasoning, coordination, and reflex—to enable safe, responsive, and resilient autonomous operation. From robotics and drones to software-defined vehicles and ADAS, the Neural Axis addresses one of physical AI’s greatest challenges: real-time decision making under strict latency and safety constraints. This presentation explores how biologically inspired distributed computing can eliminate single points of failure, accelerate response times, and provide the scalable foundation required for the next generation of intelligent machines. For more details on our speakers and to register for the event go to https://lnkd.in/ex4Qyg_H
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Bart Plackle reacted on thisBart Plackle reacted on this2.5D integration, especially at leading-edge nodes, requires a tight co-development process between the ASIC design and packaging design teams from the start. The Six Semiconductor (TSS) partnered with IC-Link by imec when they took on the challenge of developing two 7nm testchips simultaneously with TSMC’s 2.5D CoWoS packaging, under a tight timeline. When a major issue surfaced three weeks before tape-out, both teams resolved it quickly and kept the project on schedule. As Richard Fung, CEO of TSS says, “Although we’re a customer of IC-Link, we’ve been treated like a partner from day one. I’m convinced that we couldn’t have managed to complete these two tape-outs on time without them.” It also highlights why IC-Link by imec’s membership in the TSMC Open Innovation Platform 3DFabric Alliance matters. It strengthens access to advanced chip integration technologies within TSMC’s 3DFabric ecosystem, including 2.5D and 3D approaches such as CoWoS. In this video, Richard Fung, Ricky L., and Ron C. from TSS explain what that means in practice for companies bringing complex chips to tape-out.Partnership The Six Semiconductor & IC Link by imec.Partnership The Six Semiconductor & IC Link by imec.
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Bart Plackle liked thisBart Plackle liked thisAm 16. Juli im IPAI Heilbronn: Auftakt zu Chip Connect BW, dem neuen Ökosystem für Halbleiter und Chips im Länd Baden-Württemberg hat das Potenzial, zu einer führenden Chip-Region Europas zu werden. Auf dem Weg, wie dies gelingt, bewegen uns unter anderem folgende Fragen: ➡️ Wie können Akteure der regionalen Halbleiterindustrie Resilienz und Autonomie entwickeln? ➡️ Welche Chancen eröffnet der European Chips Act 2.0? ➡️ Wie profitieren KMU und Startups vom Engagement großer Industrieunternehmen? ➡️ Was sind die Anforderungen an Aus- und Weiterbildung? Gemeinsam suchen wir Antworten – und schaffen in den kommenden Jahren ein Ökosystem, das optimale Bedingungen für Austausch und konkrete Lösungen bietet. Herzstück ist der Standort Heilbronn, mitten im IPAI. Feiern Sie mit uns den Projektauftakt! 🗓️ Donnerstag, 16. Juli 2026 🕑 14:30 Uhr – 20:00 Uhr 🏢 IPAI Spaces, Heilbronn Jetzt hier anmelden! https://lnkd.in/dCKvEZtS Was Sie erwartet: ✅ Der offizielle Projektstartschuss durch Herrn Ministerialdirektor Michael Kleiner, Ministerium für Wirtschaft, Handwerk und Tourismus Baden-Württemberg ✅ Impulse der Keynote-Speakers: Markus Ulm, VP BU MEMS, Robert Bosch GmbH und Dr. Peter Kürz, Head of Field of Business High-NA EUV, Zeiss Semiconductor Manufacturing Technology ✅ Vorstellung des Projekts Chip Connect BW und unserer Partner Eine Paneldiskussion rund um die Perspektiven für ein Chip-Ökosystem in Baden-Württemberg ✅ Die Präsentation der neuen Arbeitsgruppen von Chip Connect BW ✅ Ein informeller Abschluss mit Gesprächen, Fingerfood und kühlen Getränken Teilen Sie diese Einladung gerne mit Kolleginnen und Kollegen. Wir freuen uns auf Sie! #GetChipConnected
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Bart Plackle liked thisBart Plackle liked thisHumanoid robots are capturing headlines, but the real test is whether they can deliver value in the physical world. Whether it’s moving goods in warehouses, stocking shelves, or supporting manufacturing operations, scaling these systems requires advances across AI, compute, and robotics. I'm looking forward to discussing what’s needed to bring intelligent robotics to scale at the AGIBOT UK Event on 30 June. Hope to see you there.
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Bart Plackle liked thisBart Plackle liked thisVery proud and honored to receive 'The Emperor of Japan' as well our 'King Filip of Belgium here on Imec. Something i will never forget!
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Bart Plackle reacted on thisBart Plackle reacted on thisHonored to welcome His Majesty Emperor Naruhito of Japan and His Majesty King Filip of Belgium to imec in Leuven. Their visit highlights the strength of the long-standing partnership between Japan and imec — built on common ambition in semiconductor innovation and global collaboration to address shared technology challenges no single company can solve alone. What stood out in particular was their strong interest in AI and the role imec plays in building the technological foundation for tomorrow’s AI-driven era — from advanced semiconductor scaling to next-generation connectivity and computing. Together with our Japanese partners across industry and academia, we continue to push the boundaries of innovation and contribute to a more resilient, future-ready semiconductor ecosystem. As Belgium and Japan celebrate 160 years of diplomatic relations, this visit marks another meaningful step in a shared journey of trust, collaboration, and progress. #imec #Semiconductors #AI #Innovation #Japan #Belgium #GlobalCollaboration
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Jose Pozo
PREVIEW OF PIC SUMMIT EUROPE DISCUSSION TOPICS. November 4 and 5, 2025, will see the return of PIC Summit Europe at the #Evoluon in Eindhoven. Once again, the event has sold out — a strong signal of how central integrated photonics has become to the global deep-tech community. Last year’s summit brought news of a new Dutch foundry (New Origin) alongside the established SMART Photonics fab, and discussions on how rapidly photonics is converging with semiconductors. This year, expectations are even higher, with announcements involving TNO Holst Centre and High Tech Campus Eindhoven. We had a conversation last week with Eelko Brinkhoff, CEO of PhotonDelta — an Optica corporate member and frequent event partner. Since Eelko has a background in public financing (Brabantse Ontwikkelings Maatschappij (BOM)) before joining PhotonDelta we explored several key issues: What’s different at PIC Summit 2025 compared to last year’s edition? How PhotonDelta continues to support startups amid a period when the Netherlands lacks a government. What PhotonDelta gained from participating in the Global Photonics Economic Forum in Málaga, and why international collaboration is critical. Whether US policy changes — from new tariffs to shifts in H-1B visas — affect Dutch and European photonics firms looking to scale across the Atlantic. How the Brainport ecosystem around ASML compares with ecosystems led by companies such as Nvidia or TSMC. Over 700 participants are expected in Eindhoven next month— from founders to corporates, from researchers to investors. The event is not only about stage announcements, but also about the candid corridor discussions that shape the future of our industry. Optica is proud to support PIC Summit Europe alongside PhotonDelta. Our collaboration underlines a simple truth: integrated photonics is no longer an academic exercise — it is industry-critical infrastructure. Below is a short illustrated interview where Eelko previews what to expect this year. A more in-depth interview with Twan Korthorst follows soon. Onward
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Scott Bibaud
Been looking forward to sharing this one – as of today Atomera is officially working with Incize, a Belgian leader in RF and power device characterization, to accelerate GaN-on-Si for #5G and #6G infrastructure, RF, and power devices. Combining MST with Incize’s superb measurement and modelling capabilities allows us to both explore how MST enhances compound semiconductor devices, and build truly ground-breaking solutions for our customers. We’re excited to evaluate a variety of changes, from reducing parasitic effects and substrate losses to improving the interface quality between GaN and silicon. Read more on how this partnership will bridge material innovation and device-level performance: https://bwnews.pr/45WefP5
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Dov Nusimovici
💎Proud to reshare the post from DIAMFAB about our participation in SBDD, organized by Hasselt University and imec, this year. This edition is a special one for us. We’re more present than ever with 7 scientific contributions: 🎤 2 oral presentations : Damien Michez and Vishwajeet Maurya 📌 5 posters : Lucie Valera, Nathan Blein, Hugo RIBEIRO, Daniel Sardois and myself. 🦾 It strongly reflects our team’s determination to make diamond semiconductors and devices an industrial reality. SBDD is always a key moment to connect with the diamond community and share insights on the latest technological advances. 📣 If you’re attending SBDD, I would be very happy to connect. Come to our talks, stop by our posters, or just reach out to grab a coffee and discuss materials, devices, and future perspectives. Looking forward to seeing many of you there! 🚋 #SBDD #Diamond #PowerElectronics #Semiconductors #Innovation
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