An abstraction library for interfacing EDA tools

Repurposing existing HDL tools to help writing better code

A Python package to use FPGA development tools programmatically.

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

Container image with an open-source HDL toolchain — GHDL, Yosys, Icarus, Verilator, slang — plus waveview, a deterministic VCD/FST/GHW waveform renderer.

A possible replacement for openflow, which would be ideally contributed to the SymbiFlow project

Automation scripts for running and cleaning an Alliance-based VHDL synthesis flow using vasy, boom, boog, and loon.

Virtual Educational Design Architecture for RISC-V: An open-source platform for cycle-accurate simulation, interactive visualization, and AI-assisted analysis of RV32I processor microarchitectures.

A meta repo with numerous different templates or boilerplate projects for several languages and technologies.

This repository provides a lightweight, scalable automated verification pipeline for VHDL-based designs. It integrates GHDL (simulation) and Cocotb (Python-based verification) into GitHub Actions, ensuring that every code change is automatically validated.

Interactive FPGA board simulator with VHDL simulation via GHDL or NVC

Logimentor VHDL fixed point math library