[Kernel] Speed up silu_and_mul_per_block_quant with warp-shuffle reduction + vectorized I/O#44173
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Rewrite silu_and_mul_per_block_quant_kernel from one-thread-block-per-(token, group) with a log2(group_size) shared-memory tree reduction to one-warp-per-group with a warp-shuffle abs-max (no shared memory, no __syncthreads) and wide vectorized loads/stores (each lane owns EPT=group_size/32 contiguous elements; kWarpsPerBlock=4 groups per 128-thread block). The previous design issued one scalar bf16 load per element and serialized on log2(group_size) __syncthreads, leaving the kernel memory-latency-bound. The warp-shuffle reduction removes all barriers and shared memory; the vectorized path halves the global load/store instruction count. Numerically identical: the per-element op sequence (fp32 SiLU, fmaxf abs-max) is unchanged and fmaxf is order-invariant, so the per-group max -- and therefore every scale and quantized byte -- is bit-for-bit identical to the old kernel (verified bitwise across M=16..65536, fp8 and int8). FP16+BF16 and the VLLM_DISPATCH_* / ScaledQuant paths are unchanged. No new shape constraints: vectorized loads stay aligned for every (hidden_size, group_size) already accepted (group_size = 32*EPT divides hidden_size). H200, hidden_size=2048, group_size=128: speedup grows with M (= num_tokens * top_k) and plateaus ~2.6x at prefill scale -- M=4096 2.47x, M=16384 2.58x, M=65536 2.64x; GeoMean 2.41x for M>=512, 2.57x for M>=4096 (fp8; int8 slightly higher). Signed-off-by: SII-yangdian <yangdian@sii.edu.cn>
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Friendly ping for review 🙏 This is a performance-only rewrite of @ProExpertProg — you reviewed the original kernel (#32996) and own |
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Hi @yangdian96, the pre-commit checks have failed. Please run: uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-filesThen, commit the changes and push to your branch. For future commits, Tip Is
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Thanks a lot, nice find! I'll review in a bit and unblocked ci |
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Hi @yangdian96, the pre-commit checks have failed. Please run: uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-filesThen, commit the changes and push to your branch. For future commits, Tip Is
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This pull request has merge conflicts that must be resolved before it can be |
…k-quant-warp-shuffle
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Hi @mgoin, thanks again for labeling/unblocking CI. I resolved the merge conflict from the torch stable ABI migration and pushed the update ( Pre-commit/DCO passed; Buildkite is running here: https://buildkite.com/vllm/ci/builds/70676 Could you take another look when you get a chance? Thanks! |
mgoin
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Great work here, all checks out to me!
mgoin
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Great work here, all checks out to me!
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This broke AMD build |
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn> Signed-off-by: Ekagra Ranjan <3116519+ekagra-ranjan@users.noreply.github.com>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn> Signed-off-by: Waqar Ahmed <waqar.ahmed@amd.com>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn> Signed-off-by: divineearthly <divineearthly@gmail.com>
…rp-shuffle) + vllm-project#43014 (MoE permute pre-alloc) Two csrc CUDA kernel perf optimizations applied as source commits so the from-source build (docker/Dockerfile, real nvcc compile) actually recompiles them. These are the ones that the prior overlay-on-prebuilt-binary lineage (dsv4-tiera2/tiera3) could NOT pick up, because that lineage was a Python-source overlay on the Aiden b12x prebuilt binaries and never recompiled csrc. Applied (both verified: git apply --check clean on this eb99b8b/flat tree, on the active hot-path, real perf wins): * vllm#44173 (commit 66c1760) — Warp-shuffle + vectorized silu_and_mul_per_block_quant. Pure kernel-internal change to csrc/quantization/fused_kernels/fused_silu_mul_block_quant.cu (no binding / signature change → drop-in). Bit-identical output (verified M=16..65536 in PR), ~2.4-2.6x kernel speedup at prefill scale. On the act_quant fusion pass hot-path (act_quant_fusion.py). NOTE: the originally-cited commit c09ad76 is the kernel's ORIGINAL creation (already present in this tree); 66c1760 is the actual warp-shuffle perf commit. * vllm#43014 (net of 4107002..f90eda5, 6 target files) — MoE permute pre-allocated buffer path. Adds moe_permute_with_scratch + moe_permute_sort_workspace_size C++ ops and the MoEPermuteScratch reused- buffer wrapper, wired into cutlass_moe.py + fused_humming_moe.py. 9-14% moe_permute kernel win. Verified the new ops are actually CALLED (not dead code): moe_permute_unpermute.py:214/:71. Intentionally SKIPPED (adversarially analyzed; would be forced builds): * vllm#43162 (fused qnorm/rope/kv head-pad) — the csrc patch targets a templated switch-dispatch refactor (launchFusedDeepseekV4Templated / kNumHeadsQPadded) ABSENT from this older eb99b8b kernel, and its Python half targets the missing nested vllm/models/deepseek_v4/nvidia/ layout. Both halves fail to apply; landing it needs a full manual re-expression against a structurally different kernel + a non-existent file. (The kernel IS used here via deepseek_v4_attention.py:617, so the intent is relevant — but the patch is anchored to a tree generation we don't have.) * vllm#43554 ("router GEMM PDL") — MISLABELED. The PR is actually [Kernel] Remove NormGateLinear (a -836-line DELETION of the dsv4_norm_router_gemm kernel). Its only PDL content is incidental removal of an env-gate around pre-existing PDL in dsv3_router_gemm; it adds no GB10 PDL optimization. This tree ACTIVELY USES NormGateLinear (deepseek_v4.py self.norm_gate, norm_gate_linear.py:30) — applying it would regress, not optimize. flashinfer vllm-project#3461/vllm-project#3624 remain the JIT overlay (tiera3); this commit adds the vLLM csrc deltas that only a from-source build can realize. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…rize_with_alignment output-alignment crash guard) Adds one more adversarially-verified pick on top of 2763c4d's vllm-project#44173 + vllm-project#43014. The from-source build (real nvcc compile) recompiles this csrc header, so the fix is runtime-effective (unlike the tiera2/tiera3 prebuilt-binary overlay lineage that could not pick up csrc changes). Applied (cherry-pick 4583630, --no-commit clean, exit 0; 2 files): * vllm#45466 ([Bugfix][Kernel], merged 2026-06-18) — Check output alignment in vectorize_with_alignment. The vector load/store path goes through vec_n_t<T,VEC_SIZE> (declared __align__(VEC_SIZE*sizeof(T))), so BOTH in and out must be aligned to their own vector width. Previously only `in` was checked ("output guaranteed same as input" assumption). reshape_and_cache_ flash writes KV-cache rows at byte offsets that are a multiple of head_size; for head sizes not a multiple of VEC_SIZE this puts some `out` rows off the vector-width boundary -> vectorized store -> CUDA misaligned-address crash (issue vllm-project#41257). The fix adds an OUT_WIDTH alignment check to the fast-path predicate + a post-prefix co-alignment check that falls back to a fully scalar copy when in/out cannot be co-aligned. Bit-identical output (only chooses scalar vs vector path), strictly a hardening — never wrong, only slower on the rare unaligned row. HOT PATH confirmed in this tree: csrc/cache_kernels.cu (reshape_and_cache_ flash, the KV-cache decode write path) includes vectorization_utils.cuh and calls vectorize_with_alignment; also used by w8a8/fp8 common.cu, int8 scaled_quant.cu, layernorm_kernels.cu, layernorm_quant_kernels.cu, libtorch_stable per_token_group_quant.cu. Arch-portable header (compiles on sm_121a like every other arch). Zero downside even if DSV4's current head dims don't trip it today. Intentionally SKIPPED this round (each adversarially analyzed; all are DEAD-PATH on this GB10/sm_121a + b12x deployment, not forced builds): * b12x individual commits cb98da162 (SM120 dense FP8 GEMM) / c7089a418 / 0ff2847b0 — b12x is a PREBUILT BINARY package here (import b12x.integration, flashinfer.b12x_fused_moe), not a source tree. These SHAs exist in no fetched ref (they target the newer b12x v0.23 generation, not the eb99b8b DSV4 base). Not cherry-pickable; full v0.23 ABI absorption remains a separate effort. * flashinfer vllm-project#3640 (SM120 NVFP4 attention) — DEAD PATH. DSV4 decode routes MLA through b12x_compressed_mla_decode (prebuilt) with a sparse_mla fallback; vLLM has ZERO call sites into flashinfer's nvfp4_attention_sm120. Also in no release tag yet (main-only, post-rc2-cut). * flashinfer vllm-project#3309 (MLA decode num_heads<128 fold) — DEAD PATH. Patches flashinfer cute_dsl.attention.mla_decode, but vLLM imports flashinfer cute_dsl ONLY for MoE/GEMM (blockscaled_gemm, fused_moe). DSV4 MLA-decode is b12x/sparse_mla. No call site. * DeepGEMM vllm-project#324 (nv_dev, sm121 MQA-logits / HC-prenorm) — DEAD PATH. OPEN (not merged), against deepseek-ai/DeepGEMM nv_dev. vLLM's is_device_capability_family(120) shunt in vllm/utils/deep_gemm.py returns BEFORE native DeepGEMM _lazy_init, sending MQA-logits + HC-prenorm to hand-written Triton sm12x kernels (sm12x_mqa.py, sm12x_deep_gemm_ fallbacks.py). b12x covers the dense-GEMM/MoE surface. vllm-project#324's kernels would compile but never be called on GB10. * vllm#44217 ([Perf] dsv3_router_gemm heuristic) — DEAD PATH + out of csrc scope (Python-only). Gates the specialized kernel to is_hopper((9,0)) || is_blackwell(family 100); GB10 is sm_121a (CC 12.1) = NEITHER, so allow_dsv3_router_gemm is already False here. * vllm#43557 (E8M0 scale MXFP4 W4A4 CUTLASS) — cherry-picks clean but DEAD code on sm_121a: mxfp4_experts_quant.cu is gated to FP4_ARCHS=10.0a/10.1a/ 10.3a (ENABLE_NVFP4_SM100). GB10 MXFP4 experts use Marlin, not this kernel. * vllm-project#42996/vllm-project#46006 (PDL for DeepGEMM), vllm-project#46070 (revert vllm-project#42379), vllm-project#44109 (weightless RMSNorm), vllm-project#45277 (build-infra), torch-stable-ABI migration series [6/n]-[12/n], vllm-project#43827 (DSv4 TRTLLM attn — the vllm-project#43162 nested-layout trap) — conflict / ABI-refactor / deletion / nested b12x-v0.23 layout absent here. Methodology: clean cherry-pick != effective. The decisive gate for nearly every SKIP was CODE ROUTING, not the diff applying: this DSV4-on-GB10 build sends its hot kernels through b12x (prebuilt) + Triton sm12x fallbacks + Marlin MXFP4, while upstream CUTLASS/DeepGEMM/specialized-kernel paths are arch-gated to SM90/SM100 and do not execute on sm_121a. Picks that target those paths are no-ops here regardless of how cleanly they apply. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
…ction + vectorized I/O (vllm-project#44173) Signed-off-by: SII-yangdian <yangdian@sii.edu.cn> Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
Purpose
silu_and_mul_per_block_quant(fusedSiLU(gate) * up+ per-(token, group)FP8/INT8 quantization on the DeepSeek block-FP8 MoE expert path) is functionally
complete but has never been performance-tuned. The current kernel launches one
thread block per (token, group), does one scalar load per element, and
finds the per-group abs-max with a
log2(group_size)-level shared-memory treereduction (one
__syncthreadsper level) — which leaves it memory-latency-boundon Hopper.
This PR rewrites it as one warp per group:
EPT = group_size / 32contiguous elements;__shfl_xor_syncbutterfly — no sharedmemory, no
__syncthreads;gate/upare read with one coalesced wide vector load per lane and thequantized result written with one wide vector store;
kWarpsPerBlock = 4groups are packed into each 128-thread block.The output is bit-for-bit identical to the current kernel, not merely within
tolerance: the per-element op sequence (fp32 SiLU via
expf,fmaxfabs-max) isunchanged, and
fmaxfis order-invariant, so every scale and every quantized byteis identical — only the parallel mapping changes. No API or behavior change (FP16 +
BF16, FP8 + INT8,
scale_ub,is_scale_transposedare all preserved); no newshape constraints. The rewrite uses only portable intrinsics (
__shfl_xor_sync,wide vector loads/stores), so the speedup is algorithmic rather than Hopper-
specific. This is a performance-only change with no functional issue to link.
Test Plan
from the old and new kernels on identical inputs across
M = num_tokens × top_k ∈ {16, 64, 128, 256, 512, 1024, 4096, 16384, 65536},for both FP8 and INT8, and compare with
torch.equal.hidden_size = 2048,group_size = 128, BF16 input;kernel-only CUDA
device_timefor the old vs new kernel, swept over theproduction
Mrange (decode → prefill).Test Result
Existing unit test —
pytest tests/kernels/core/test_fused_silu_mul_block_quant.pyon H200 (torch 2.11.0+cu130): 650 passed (FP16/BF16 × FP8/INT8 ×
group_size64/128 ×
is_scale_transposed× all shapes, plusopcheck).Bitwise-identical output for every
Mand dtype tested: identical quantizedbytes and identical scales (
max |Δscale| = 0) — the rewrite changes no outputbit, so it passes the suite above exactly as the kernel on
maindoes.Performance (H200, FP8, kernel-only
device_time):GeoMean 2.41× over M ∈ [512, 65536] (2.57× for M ≥ 4096, prefill), peak
2.65× (FP8) / 2.77× (INT8) at M = 131072. Speedup grows with
Mand plateausat ~2.6–2.8× as the kernel becomes throughput-bound; small-
Mdecode shapesshow no regression.
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