[ROCm][gpt-oss] Hybrid CDNA4 swizzle gate for A8W4 MoE#44804
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Signed-off-by: Xiaohu Guo <Xiaohu.Guo@amd.com>
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The MXFP4 W4A16 weight-load path in oracle/mxfp4.py uses shuffle_weight_a16w4 (is_guinterleave=True), which interleaves gate/up columns within each weight tile. The CK/FlyDSL MoE kernels in aiter must be told this via gate_mode=GateMode.INTERLEAVE so they decode the gate/up packing correctly. Without the explicit gate_mode, aiter defaults to SEPARATED and (since ROCm/aiter#3123) dispatches the (SEPARATED + Swiglu + per_1x32 + fp4x2) case to a path that returns garbage for shuffled weights or crashes during CK2stages JIT for the unshuffled Quark variant (amd/gpt-oss-20b-w-mxfp4-a-bf16). This was the root cause of ROCM-25517 (gpt-oss-120b W4A16 gsm8k acc = 0) and ROCM-25478 (gpt-oss-20b Quark JIT crash). Other paths are unaffected: - FP8 W8A8 (DeepSeek-V4-Pro, DeepSeek-V3.2): shuffled with quark_ocp_mx.py:shuffle_weight(layout=(16,16)) — non-interleaved. use_mxfp4_w4a16 is False, default SEPARATED preserved. - MXFP4 W4A4 (amd/DeepSeek-R1-0528-MXFP4): shuffled via rocm_aiter_ops.shuffle_weights — non-interleaved. use_mxfp4_w4a16 is False, default SEPARATED preserved. The gate_mode kwarg was added to aiter.fused_moe in ROCm/aiter#3123 (aiter>=0.1.14). To stay compatible with older aiter shipping with vllm (e.g. aiter 0.1.13.post1 in the vllm-rocm:nightly image), we probe the aiter signature and drop the kwarg when unsupported — pre-vllm-project#3123 aiter tolerated the implicit SEPARATED default for interleave-shuffled weights, so dropping the kwarg is safe there. GateMode itself only exists on aiter>=0.1.14 and is imported under try/except for the same reason. Validation on MI355X (gfx950): vllm@main + aiter@main (6aeba41) openai/gpt-oss-120b W4A16 gsm8k: TP=1: 0.000 -> 0.905 TP=8: 0.000 -> 0.905 vllm@main + aiter@main amd/gpt-oss-20b-w-mxfp4-a-bf16 TP=2 enforce-eager: CK2stages JIT crash -> serves cleanly vllm-rocm:nightly + aiter 0.1.13.post1 openai/gpt-oss-120b W4A16 gsm8k: TP=1: 0.910 (backward-compat — gate_mode kwarg silently dropped) vllm-rocm:v0.22.0 + aiter@main openai/gpt-oss-120b W4A16 gsm8k: TP=1: 0.895 amd/gpt-oss120b-w-mxfp4-a-fp8 W4A8 (this PR composes with vllm-project#44804): TP=8 mc=1=326, mc=8=2087, mc=32=6523, mc=64=11610 tok/s Reference: sgl-project/sglang#25580 (sglang's equivalent fix). Recommended by aiter maintainer (XiaobingZhang) on ROCm/aiter#3586. Signed-off-by: Rohan Potdar <rohan.potdar@amd.com>
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tensor_model_parallel_world_size() <= 2in both places (falls back toStridedLayoutfor TP>=4). TP=1/2unchanged.
should_use_cdna4_mx_scale_swizzle()so they can't drift — a mismatch between the weight-load layout and the kernel'sswizzle_mx_scale=arg silently corrupts the scale tensor.BLOCK_K>=256constraint (so swizzle-on gets a fair shot), the strided layout still wins 23/28 cells in the standard sweep — up to +19% on decode-heavy 1K/1K. Swizzle-on only wins at the very-high-concurrency 8K/1K corner