[Bugfix] Defer block freeing until in-flight steps finish under async scheduling + PD KV consumer

[llx-08]

Summary

This PR fixes a race in async scheduling with PD KV consumers by deferring the actual return of freed KV blocks to the block pool until the newest in-flight scheduled step has finished.

With async scheduling, the scheduler may dispatch step N+1 before step N's output is processed. If a request finishes or is preempted based on step N's output, step N+1 may already be in flight and may still write to that request's KV blocks. If those blocks are immediately returned to the block pool and reallocated to a request receiving KV via PD, the NIC/RDMA write that fills the new request's KV is not ordered with respect to the stale in-flight GPU write from the old request. The stale GPU write can therefore corrupt the newly received KV/state.

The fix keeps request bookkeeping cleanup immediate, but defers the ref-count decrement / block-pool return until update_from_output() observes that the fence step's output has been processed.

Problem Timeline

A problematic sequence looks like this:

1. Scheduler dispatches step N for request R.
2. Async scheduling dispatches step N+1 before step N's output is processed.
3. Step N output returns, and request R is found to be finished, stopped, or preempted.
4. The old code immediately frees R's KV blocks back to the block pool.
5. A new PD consumer request reuses those blocks and receives KV/state via NIC/RDMA.
6. Step N+1, which was already in flight for R, later writes stale data into the same blocks.
7. The new request's received KV/state is corrupted.

The important part is that the PD receive path fills cache blocks via external transfer, while the stale write is produced by GPU compute. These operations are not naturally ordered by the CUDA stream used for model execution.

Implementation

This PR separates "removing a request's ownership of blocks" from "returning those blocks to the reusable block pool".

Step Fences

SchedulerOutput now carries a scheduler step sequence number, sched_seq.

The scheduler increments _sched_step_seq only for non-empty scheduled steps, and stores that value in the corresponding SchedulerOutput.

When update_from_output() receives a model runner output, it updates _processed_step_seq from scheduler_output.sched_seq. This tells the scheduler which scheduled step has completed and had its output processed.

Deferred Free Queue

The scheduler maintains a queue of deferred block frees:

_deferred_frees: deque[tuple[int, list[KVCacheBlock]]]

Each entry is:

(fence_seq, blocks)

fence_seq means that these blocks can be returned to the pool only after scheduler output for this step has been processed.

For example, if request R finishes while _sched_step_seq == 2, then R's blocks are queued as (2, R_blocks). When _processed_step_seq >= 2, all GPU writes from step 2 and earlier have completed, so those blocks can be safely returned to the block pool.

Split Block Cleanup

This PR adds pop_blocks_for_free() through the KV cache manager stack:

• SingleTypeKVCacheManager.pop_blocks_for_free()
• KVCacheCoordinator.pop_blocks_for_free()
• KVCacheManager.pop_blocks_for_free()

pop_blocks_for_free() removes request bookkeeping immediately, such as req_to_blocks and cached-block metadata, and returns the blocks without calling block_pool.free_blocks().

The original free() path is preserved by implementing it on top of pop_blocks_for_free(). This keeps existing immediate-free behavior unchanged when deferral is disabled.

Scheduler Free Path

Finished and preempted requests now go through a shared scheduler helper, _free_request_blocks(request).

If deferral is disabled, or if there is no in-flight scheduled step, it frees immediately.

If deferral is enabled and there is still an in-flight step, it:

1. Pops the request's block bookkeeping immediately.
2. Records the blocks in _deferred_frees.
3. Uses the current _sched_step_seq as the fence.

Then update_from_output() drains entries whose fence has completed: fence_seq <= _processed_step_seq.

When It Is Enabled

The deferral is enabled only for:

async_scheduling && kv_consumer

This keeps the change scoped to the case where the scheduler may have already dispatched an in-flight step and the instance may receive externally written KV blocks.

Why This Matters

This race is especially visible for hybrid / mamba-style caches because an in-flight step can rewrite a whole state block every step. If such a block is reused by a PD consumer request, the stale write can overwrite the entire received state and cause severe output corruption.

The same ordering issue can also affect full-attention KV blocks. In that case the stale write is usually limited to the newly written token KV slot, so the corruption is smaller and may be harder to observe at the request level, but the underlying race is the same.

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[ZJY0516]

@llx-08 please provide the accuracy test result

[njhill]

Thanks for this @llx-08. Like @ZJY0516 said, it would be very helpful if you have a reproducer for this!

[NickLucche]

@njhill Alternative approach to #45096, we were able to repro with PD mamba tp>1 pretty consistently.
So yeah absolutely, we want to check lm-eval jitter over N runs for this issue

[njhill]

@llx-08 I have made some simplifications and added a test here, PTAL: njhill@d1c0d16

[njhill]

I think this is actually applicable to most connectors, not just PD/nixl.

[llx-08]

@llx-08 I have made some simplifications and added a test here, PTAL: njhill@d1c0d16

Thanks! I'll cherry-pick your commit and run accuracy tests together.

[llx-08]

@ZJY0516 @njhill Hi, I ran tests on the GSM8K dataset comparing the baseline and the PR-applied code. The accuracy looks correct, with some minor fluctuations.

Metrics	Baseline (No-PD)	Disagg v1 (894c41d)	Disagg v2 (d1c0d16)
Accuracy	0.86	0.88	0.85
Invalid rate	0.0	0.0	0.0
Latency	32.74s	27.01s	27.00s
QPS	3.05	3.70	3.70
Tokens/s	454.8	563.3	566.6

[njhill]

Thanks @llx-08. I just pushed another commit to also cover PP cases which I think still had a similar exposure because of how we schedule multiple steps ahead (with or without async enabled).

But accidentally pushed to your branch this time, I hope that's ok. Perhaps you could run the eval one last time? Then we can get this merged...

[ZJY0516]

please also update the test here

vllm/tests/v1/kv_connector/nixl_integration/config_sweep_accuracy_test.sh

Lines 25 to 32 in 2c764c0

	hybrid_ssm_configs=(
	"VLLM_SSM_CONV_STATE_LAYOUT=DS GPU_MEMORY_UTILIZATION=0.8 MODEL_NAMES=ibm-granite/granite-4.0-h-tiny VLLM_SERVE_EXTRA_ARGS=--max-model-len,8192,--trust-remote-code"
	# TODO: (NickLucche) Address async scheduling issue with TP>1 separately as this may impact other models.
	"VLLM_SSM_CONV_STATE_LAYOUT=DS PREFILLER_TP_SIZE=2 DECODER_TP_SIZE=2 GPU_MEMORY_UTILIZATION=0.8 MODEL_NAMES=ibm-granite/granite-4.0-h-tiny VLLM_SERVE_EXTRA_ARGS=--max-model-len,8192,--trust-remote-code,--no-async-scheduling"
	# GDN (Qwen3.5)
	"VLLM_SSM_CONV_STATE_LAYOUT=DS GPU_MEMORY_UTILIZATION=0.8 MODEL_NAMES=Qwen/Qwen3.5-0.8B"
	"VLLM_SSM_CONV_STATE_LAYOUT=DS PREFILLER_TP_SIZE=1 DECODER_TP_SIZE=2 GPU_MEMORY_UTILIZATION=0.8 MODEL_NAMES=Qwen/Qwen3.5-0.8B VLLM_SERVE_EXTRA_ARGS=--no-async-scheduling"
	)

[llx-08]

Thanks @llx-08. I just pushed another commit to also cover PP cases which I think still had a similar exposure because of how we schedule multiple steps ahead (with or without async enabled).

But accidentally pushed to your branch this time, I hope that's ok. Perhaps you could run the eval one last time? Then we can get this merged...

No worries, thank you very much!
I ran the accuracy test with 99c4e1a, and the results are below:

Metrics	Baseline (No-PD)	Disagg (99c4e1a)
Accuracy	0.87	0.88
Invalid rate	0.0	0.0
Latency	31.14s	29.38s
QPS	3.21	3.40
Tokens/s	487.2	500.7

(There are some differences from the previous results. Previously, I picked the changes onto v0.19.0 for testing; this time, I reran the test with the new v0.23.0 image.)
@ZJY0516 I update vllm/tests/v1/kv_connector/nixl_integration/config_sweep_accuracy_test.sh, not disabling async-scheduling in test.

[ZJY0516]

Thanks!

[NickLucche]

Thanks to everyone here for fixing this race!

[arpera]

Could someone explain to me how to reproduce these results?

If I understand right, this PR is intended to fix this issue #37285
I tested this patch locally and I see the same low accuracy as it was before the fix:

Running GSM8K evaluation: 1319 questions, 5-shot
Evaluating: 100%
1319/1319 [00:46<00:00, 28.24it/s]

Results:
Accuracy: 0.108
Invalid responses: 0.109
Total latency: 46.717 s
Questions per second: 28.234
Total output tokens: 316112
Output tokens per second: 6766.509

At the same time if I disable async scheduling on decode side, then accuracy is good:

Running GSM8K evaluation: 1319 questions, 5-shot
Evaluating: 100%
1319/1319 [00:38<00:00, 34.03it/s]

Results:
Accuracy: 0.851
Invalid responses: 0.000
Total latency: 38.766 s
Questions per second: 34.024
Total output tokens: 190059
Output tokens per second: 4902.695

Steps to reproduce:

# prefill
VLLM_SSM_CONV_STATE_LAYOUT=DS \
VLLM_NIXL_SIDE_CHANNEL_HOST="$(hostname)" \
VLLM_NIXL_SIDE_CHANNEL_PORT=6550 \
vllm serve Qwen/Qwen3.5-35B-A3B \
  --served-model-name Qwen3.5-35B-A3B \
  --host 0.0.0.0 --port 8100 \
  -tp 1 --generation-config vllm --no-enable-prefix-caching --no-disable-hybrid-kv-cache-manager \
  --async-scheduling \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_both","kv_load_failure_policy":"fail"}'

# decode
VLLM_SSM_CONV_STATE_LAYOUT=DS \
VLLM_NIXL_SIDE_CHANNEL_HOST="$(hostname)" \
VLLM_NIXL_SIDE_CHANNEL_PORT=6551 \
vllm serve Qwen/Qwen3.5-35B-A3B \
  --served-model-name Qwen3.5-35B-A3B \
  --host 0.0.0.0 --port 8200 \
  -tp 1 --generation-config vllm --no-enable-prefix-caching --no-disable-hybrid-kv-cache-manager \
  --async-scheduling \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_both","kv_load_failure_policy":"fail"}'

# router
python tests/v1/kv_connector/nixl_integration/toy_proxy_server.py \
  --host 0.0.0.0 --port 8000 \
  --prefiller-hosts "$PREFILL_HOST" --prefiller-ports 8100 \
  --decoder-hosts "$DECODE_HOST" --decoder-ports 8200

# gsm8k test
python tests/evals/gsm8k/gsm8k_eval.py

[llx-08]

Could someone explain to me how to reproduce these results?

If I understand right, this PR is intended to fix this issue #37285 I tested this patch locally and I see the same low accuracy as it was before the fix:

Running GSM8K evaluation: 1319 questions, 5-shot
Evaluating: 100%
1319/1319 [00:46<00:00, 28.24it/s]

Results:
Accuracy: 0.108
Invalid responses: 0.109
Total latency: 46.717 s
Questions per second: 28.234
Total output tokens: 316112
Output tokens per second: 6766.509

At the same time if I disable async scheduling on decode side, then accuracy is good:

Running GSM8K evaluation: 1319 questions, 5-shot
Evaluating: 100%
1319/1319 [00:38<00:00, 34.03it/s]

Results:
Accuracy: 0.851
Invalid responses: 0.000
Total latency: 38.766 s
Questions per second: 34.024
Total output tokens: 190059
Output tokens per second: 4902.695

Steps to reproduce:

# prefill
VLLM_SSM_CONV_STATE_LAYOUT=DS \
VLLM_NIXL_SIDE_CHANNEL_HOST="$(hostname)" \
VLLM_NIXL_SIDE_CHANNEL_PORT=6550 \
vllm serve Qwen/Qwen3.5-35B-A3B \
  --served-model-name Qwen3.5-35B-A3B \
  --host 0.0.0.0 --port 8100 \
  -tp 1 --generation-config vllm --no-enable-prefix-caching --no-disable-hybrid-kv-cache-manager \
  --async-scheduling \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_both","kv_load_failure_policy":"fail"}'

# decode
VLLM_SSM_CONV_STATE_LAYOUT=DS \
VLLM_NIXL_SIDE_CHANNEL_HOST="$(hostname)" \
VLLM_NIXL_SIDE_CHANNEL_PORT=6551 \
vllm serve Qwen/Qwen3.5-35B-A3B \
  --served-model-name Qwen3.5-35B-A3B \
  --host 0.0.0.0 --port 8200 \
  -tp 1 --generation-config vllm --no-enable-prefix-caching --no-disable-hybrid-kv-cache-manager \
  --async-scheduling \
  --kv-transfer-config '{"kv_connector":"NixlConnector","kv_role":"kv_both","kv_load_failure_policy":"fail"}'

# router
python tests/v1/kv_connector/nixl_integration/toy_proxy_server.py \
  --host 0.0.0.0 --port 8000 \
  --prefiller-hosts "$PREFILL_HOST" --prefiller-ports 8100 \
  --decoder-hosts "$DECODE_HOST" --decoder-ports 8200

# gsm8k test
python tests/evals/gsm8k/gsm8k_eval.py

Hi, @arpera ,I have done some experiments, the accuracy drop (0.108–0.480 on GSM8K) when using PD disaggregation with async scheduling is caused by a race condition between zero_blocks and RDMA transfers in the model runner.

Root Cause

In async scheduling mode (batch_queue_size=2), execute_model(B2) begins while forward(B1) is still running on the default CUDA stream. The following sequence causes data corruption:

1. _update_states(B2) submits zero_blocks to the CUDA stream → queued behind forward(B1)
2. start_load_kv initiates RDMA transfer via GPUDirect DMA — this bypasses the CUDA stream entirely
3. RDMA completes quickly, writing P's attention KV cache data into D's newly-allocated blocks
4. CUDA stream finally reaches zero_blocks → overwrites the RDMA-loaded KV data with zeros
5. forward(B2) runs with zeroed attention KV cache → 10 full-attention layers (out of 40 total layers) lose all prefill context

The KVBlockZeroer only zeros FullAttentionSpec layers (Mamba/GDN state blocks are skipped), so the 10 attention layers' KV cache is wiped while the 30 GDN layers retain their state. This partial context loss explains why the model still produces semi-coherent but incorrect outputs rather than complete garbage.

Experiment

Configuration	Accuracy (GSM8K 50Q, 5-shot)	Notes
Single-node + async	0.900	No RDMA involved
PD + no-async	0.900-0.920	No pending forward, zero_blocks runs immediately
PD + async, sequential (concurrency=1)	0.900	1 request per batch, no race
PD + async, concurrency=2	0.833	Race begins
PD + async, concurrency=5	0.700
PD + async, concurrency=10	0.667
PD + async, concurrency=30	0.567
PD + async, default concurrency (50Q)	0.480
PD + async, packed decode disabled	0.540	Ruled out packed decode kernel
PD + async, CUDA sync after RDMA	0.500	Doesn't fix - syncs wrong ordering
PD + async, torch.cuda.synchronize() before start_load_kv	0.900	Confirms root cause
PD + async, needs_kv_cache_zeroing=False	0.900	Clean fix, zero overhead

Actually, if you are using Flashattn3, there is no need to use zeroing. Zeroing is only necessary when using FA4 or Flashinfer.

Regarding this issue, my solution is to skip zeroing on the D node, and instead let the data transferred from the P node overwrite the stale data on the D node.

BTW, is this a known problem? Should we fix it? @njhill @NickLucche @ZJY0516

[arpera]

@llx-08 could you please tell me is it right that this PR is intended to fix issue #37285?

[llx-08]

@llx-08 could you please tell me is it right that this PR is intended to fix issue #37285?

This PR fixes a conflict between async scheduling and PD KV cache transfer on the decode side. I noticed someone commented "prefill async is fine" in #37285, so I believe this PR would likely fix that issue as well.
However, the accuracy degradation you reported is caused by a different root cause — zero_blocks overwrites the KV cache data received by the decode node via RDMA, which is unrelated to the block-reuse race that this PR addresses.

[ZJY0516]

BTW, is this a known problem? Should we fix it

yes, see this #45096 (comment)

[llx-08]

BTW, is this a known problem? Should we fix it

yes, see this #45096 (comment)

Hi, I've created a related PR:#47373, please help me review the code. Thanks♥️