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[ROCm][P/D] Support MiniMax-M3 mixed KV layouts in MoRIIO READ mode#46039

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junkang1991:fix-mori-connector-minimaxm3
Jun 21, 2026
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[ROCm][P/D] Support MiniMax-M3 mixed KV layouts in MoRIIO READ mode#46039
DarkLight1337 merged 10 commits into
vllm-project:mainfrom
junkang1991:fix-mori-connector-minimaxm3

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@junkang1991

@junkang1991 junkang1991 commented Jun 18, 2026

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Purpose

Fix MoRIIO READ-mode KV transfer when a model uses mixed per-layer KV cache layouts, observed with MiniMax-M3.

MiniMax-M3 registers multiple KV cache layouts:

  • separated K/V cache: [2, num_blocks, block_size, num_kv_heads, head_dim]
  • ROCm interleaved K/V cache: [num_blocks, 2, block_size, num_kv_heads, head_dim]
  • 3D key-only / MLA indexer cache: [num_blocks, block_size, head_dim]

MoRIIO previously reused layout assumptions and READ transfer offsets derived from one representative layer. That can read or register the wrong memory region when dense K/V layers and 3D key-only/indexer layers are mixed, causing corrupted decode output in P/D disaggregated serving.

This PR makes MoRIIO READ layout handling per-layer and layout-aware.

Fixes #45885.

Scope

This PR only fixes MoRIIO READ-mode per-layer KV layout handling.

It does not include:

  • WRITE-mode per-geometry offset caching.
  • heterogeneous TP rank mapping / duplicate ACK handling.

Changes

  • Add layout-aware MoRIIO KV cache helpers.
  • Preserve support for separated K/V layout: [2, num_blocks, block_size, heads, dim].
  • Add support for ROCm interleaved K/V layout: [num_blocks, 2, block_size, heads, dim].
  • Add support for 3D key-only / MLA indexer cache layout.
  • Register KV cache memory regions using the actual layer layout.
  • Compute READ transfer offsets per layer instead of reusing offsets from the first layer.
  • Use KVCacheSpec to identify MLA/key-only layers; tensor shape/stride is used only for physical offset computation.
  • Add focused unit tests for offset computation and registration region behavior.

Validation

Unit / static checks

  • Added coverage in tests/v1/kv_connector/unit/test_moriio_kv_layout.py.
  • Existing MoRIIO connector unit coverage updated.
  • git diff --check passed.

Test Plan

Tested MiniMax-M3 MXFP8 on an 8x MI355X intranode setup with 1P1D PD disaggregation:

  • Prefill: TP4 on GPUs 0,1,2,3
  • Decode: TP4 on GPUs 4,5,6,7
  • Proxy: vllm-router
  • KV connector: MoRIIO READ mode
  • MoRIIO backend: XGMI

Start vLLM router

docker run --rm --network host vllm/vllm-router:nightly \
  vllm-router \
  --host 127.0.0.1 \
  --port 30000 \
  --vllm-pd-disaggregation \
  --kv-connector moriio \
  --vllm-discovery-address "0.0.0.0:36367"

Start prefill instance

HIP_VISIBLE_DEVICES=0,1,2,3 \
vllm serve /app/model/MiniMaxAI__Minimax-M3-preview__mxfp8 \
  --served-model-name MiniMaxAI/MiniMax-M3-MXFP8 \
  --host 0.0.0.0 \
  --port 8100 \
  --tensor-parallel-size 4 \
  --block-size 128 \
  --trust-remote-code \
  --kv-transfer-config '{
    "kv_connector": "MoRIIOConnector",
    "kv_role": "kv_producer",
    "kv_connector_extra_config": {
      "host_ip": "165.245.143.170",
      "proxy_ip": "127.0.0.1",
      "proxy_ping_port": 36367,
      "http_port": 8100,
      "handshake_port": 6301,
      "notify_port": 6105,
      "read_mode": true,
      "backend": "xgmi"
    }
  }'

Start decode instance

HIP_VISIBLE_DEVICES=4,5,6,7 \
vllm serve /app/model/MiniMaxAI__Minimax-M3-preview__mxfp8 \
  --served-model-name MiniMaxAI/MiniMax-M3-MXFP8 \
  --host 0.0.0.0 \
  --port 8200 \
  --tensor-parallel-size 4 \
  --block-size 128 \
  --trust-remote-code \
  --kv-transfer-config '{
    "kv_connector": "MoRIIOConnector",
    "kv_role": "kv_consumer",
    "kv_connector_extra_config": {
      "host_ip": "165.245.143.170",
      "proxy_ip": "127.0.0.1",
      "proxy_ping_port": 36367,
      "http_port": 8200,
      "handshake_port": 7301,
      "notify_port": 7501,
      "read_mode": true,
      "backend": "xgmi"
    }
  }'

Run GSM8K lm-eval

lm_eval run \
  --model local-chat-completions \
  --model_args "model=MiniMaxAI/MiniMax-M3-MXFP8,base_url=http://localhost:30000/v1/chat/completions,tokenizer=/app/model/MiniMaxAI__Minimax-M3-preview__mxfp8,num_concurrent=<C>" \
  --tasks gsm8k \
  --num_fewshot 5 \
  --apply_chat_template \
  --batch_size 1 \
  --gen_kwargs '{"max_tokens":4096}' 

Test Results

GSM8K 5-shot full run, 1319 examples:

Task Version Filter n-shot Metric Value Stderr
gsm8k 3 flexible-extract 5 exact_match 0.9545 0.0057
gsm8k 3 strict-match 5 exact_match 0.9553 0.0057

RDMA E2E

Validated MiniMax-M3 BF16 on an 8x MI350X node using MoRIIO READ mode over RDMA P/D:

  • Prefill: TP4 on GPUs 0-3
  • Decode: TP4 on GPUs 4-7

Results:

  • metabench_gsm8k, 237 samples:
    • flexible exact match: 0.9831223628691983
    • strict exact match: 0.9831223628691983
  • metabench_gsm8k_secondary, 249 samples:
    • flexible exact match: 0.9558232931726908
    • strict exact match: 0.9518072289156626

This PR is co-authored by
@vllmellm @hongxiayang @junkang1991 @tanpinsiang @chunfangamd @TianDi101 @functionstackx.

junkang1991 and others added 2 commits June 18, 2026 10:32
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>

Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>

Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
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@mergify mergify Bot added rocm Related to AMD ROCm kv-connector labels Jun 18, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD Jun 18, 2026
@tjtanaa

tjtanaa commented Jun 18, 2026

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@inkcherry @dllehr-amd could you help to review this? This is to fix the PD disaggregation for minimax m3 models.

@hongxiayang

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cache_list = [cache_or_caches] if use_mla else cache_or_caches
for layer_name, cache_or_caches in kv_caches.items():
# Some models register both 5D K/V caches and 3D key-only side
# caches. Only separated 5D K/V caches should be split into K and V

@inkcherry inkcherry Jun 18, 2026

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thanks for the fix! @junkang1991
One suggestion: Could we use some classes or standard judgment methods for this? for example, could we pass in kv_cache_config and use the per-layer spec to drive the classification, instead of inferring the layout from tensor shapes?

The connector already receives kv_cache_config in MoRIIOConnector.__init__, so it just needs to be forwarded to the worker:

self.connector_worker = MoRIIOConnectorWorker(
    vllm_config, self.engine_id, self.kv_cache_config
)

Then the worker can build an authoritative layer_name -> KVCacheSpec map:

def __init__(self, vllm_config, engine_id, kv_cache_config):
    ...
    self.kv_cache_config = kv_cache_config
    # layer_name -> KVCacheSpec (authoritative type info)
    self.layer_to_spec = {
        layer_name: group.kv_cache_spec
        for group in kv_cache_config.kv_cache_groups
        for layer_name in group.layer_names
    }

And classify each layer from its spec rather than from shape:

from vllm.v1.kv_cache_interface import MLAAttentionSpec, FullAttentionSpec

for layer_name, kv_cache in kv_caches.items():
    spec = self.layer_to_spec[layer_name]
    is_mla = isinstance(spec, MLAAttentionSpec)
    # Derive block_len from the spec instead of math.prod(shape)
    self.block_lens[layer_name] = spec.page_size_bytes // (...)

This way "is this layer MLA / key-only?" comes from the spec rather than from len(shape) == 3

Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>

Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
@junkang1991

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Hi @inkcherry,

The connector now uses KVCacheSpec to identify MLA cache layers instead of relying only on tensor shape. Tensor shape/stride is only used for physical offset computation.

Verified MiniMax-M3 MXFP8 on 8x MI355X, 1P1D TP4+TP4, MoRIIO READ mode with XGMI. GSM8K 5-shot full run result is ~0.955 exact match.

Also verified Qwen3-235B-A22B-FP8 with the same MoRIIO READ mode + XGMI setup to make sure the existing dense K/V path is not regressed. GSM8K 5-shot full run result:

  • flexible-extract exact_match: 0.8863 ± 0.0087
  • strict-match exact_match: 0.7415 ± 0.0121
tanpinsiang and others added 2 commits June 19, 2026 16:42
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>
Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Co-authored-by: Jun Kang Chow <junkangchow@gmail.com>
Co-authored-by: Chun Fang <chun.fang@amd.com>
Co-authored-by: TianDi101 <ditian12@amd.com>
Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Refactor MoRIIO KV layout offsets and add unit tests
@mergify mergify Bot added the v1 label Jun 20, 2026

tanpinsiang commented Jun 20, 2026

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For visibility, we have two follow-up MoRIIO branches staged on top of this READ-layout fix, from SemiAnalysisAI/InferenceX#1762 but we are not opening them against upstream main until this PR lands so their diffs stay clean.

After this PR merges, we plan to rebase each branch onto upstream main and open them as separate small PRs. PR2 and PR3 are independent of each other, but both depend on this READ-layout helper/refactor for clean ordering.

@junkang1991 junkang1991 changed the title [ROCm][P/D] Fix MoRIIO READ transfer for MiniMax-M3 Jun 20, 2026
@junkang1991

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Verified the updated commit with end-to-end lm-eval GSM8K runs using MoRIIO READ mode with the XGMI and RDMA backend on an 8x MI355X intranode 1P1D TP4+TP4 setup.

Results:

  • MiniMax-M3 MXFP8 (XGMI)

    • flexible-extract: 0.9530 ± 0.0058
    • strict-match: 0.9538 ± 0.0058
  • MiniMax-M3 MXFP8 (RDMA)

    • flexible-extract: 0.9575 ± 0.0056
    • strict-match: 0.9583 ± 0.0055
  • Qwen3-235B-A22B-FP8: (XGMI)

    • flexible-extract: 0.8848 ± 0.0088
    • strict-match: 0.7566 ± 0.0118
  • Qwen3-235B-A22B-FP8: (RDMA)

    • flexible-extract: 0.8878 ± 0.0087
    • strict-match: 0.7392 ± 0.0121
@tanpinsiang

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Ran MLA model DeepSeek-V2-Chat-0628
TP4+TP4 PD

Eval: GSM8K full, 25-shot, num_concurrent=32

Results:

Backend Status flexible-extract strict-match samples
XGMI PASS 0.8278999241849886 0.6868840030326004 1319
RDMA PASS 0.821076573161486 0.6755117513267627 1319
@tjtanaa tjtanaa added ready ONLY add when PR is ready to merge/full CI is needed verified Run pre-commit for new contributors without triggering other tests labels Jun 20, 2026
@mergify

mergify Bot commented Jun 20, 2026

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Hi @junkang1991, the pre-commit checks have failed. Please run:

uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-files

Then, commit the changes and push to your branch.

For future commits, pre-commit will run automatically on changed files before each commit.

Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>

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LGTM

mergify Bot and others added 2 commits June 20, 2026 15:54
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
@DarkLight1337 DarkLight1337 enabled auto-merge (squash) June 21, 2026 07:13
@DarkLight1337 DarkLight1337 merged commit b91b772 into vllm-project:main Jun 21, 2026
74 of 75 checks passed
@github-project-automation github-project-automation Bot moved this from Todo to Done in AMD Jun 21, 2026
tunglinwood pushed a commit to tunglinwood/vllm that referenced this pull request Jun 22, 2026
…llm-project#46039)

Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>
Co-authored-by: Chun Fang <chun.fang@amd.com>
Co-authored-by: TianDi101 <ditian12@amd.com>
Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
nkzhenhua pushed a commit to nkzhenhua/vllm that referenced this pull request Jun 24, 2026
…llm-project#46039)

Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>
Co-authored-by: Chun Fang <chun.fang@amd.com>
Co-authored-by: TianDi101 <ditian12@amd.com>
Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
qli88 pushed a commit to qli88/vllm that referenced this pull request Jun 26, 2026
…llm-project#46039)

Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: Hongxia Yang <hongxia.yang@amd.com>
Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com>
Co-authored-by: Chun Fang <chun.fang@amd.com>
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Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Signed-off-by: Qiang Li <qiang.li2@amd.com>
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kv-connector ready ONLY add when PR is ready to merge/full CI is needed rocm Related to AMD ROCm v1 verified Run pre-commit for new contributors without triggering other tests

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