[ROCm][P/D] Support MiniMax-M3 mixed KV layouts in MoRIIO READ mode#46039
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Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
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@inkcherry @dllehr-amd could you help to review this? This is to fix the PD disaggregation for minimax m3 models. |
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cc @TianDi101 |
| cache_list = [cache_or_caches] if use_mla else cache_or_caches | ||
| for layer_name, cache_or_caches in kv_caches.items(): | ||
| # Some models register both 5D K/V caches and 3D key-only side | ||
| # caches. Only separated 5D K/V caches should be split into K and V |
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thanks for the fix! @junkang1991
One suggestion: Could we use some classes or standard judgment methods for this? for example, could we pass in kv_cache_config and use the per-layer spec to drive the classification, instead of inferring the layout from tensor shapes?
The connector already receives kv_cache_config in MoRIIOConnector.__init__, so it just needs to be forwarded to the worker:
self.connector_worker = MoRIIOConnectorWorker(
vllm_config, self.engine_id, self.kv_cache_config
)Then the worker can build an authoritative layer_name -> KVCacheSpec map:
def __init__(self, vllm_config, engine_id, kv_cache_config):
...
self.kv_cache_config = kv_cache_config
# layer_name -> KVCacheSpec (authoritative type info)
self.layer_to_spec = {
layer_name: group.kv_cache_spec
for group in kv_cache_config.kv_cache_groups
for layer_name in group.layer_names
}And classify each layer from its spec rather than from shape:
from vllm.v1.kv_cache_interface import MLAAttentionSpec, FullAttentionSpec
for layer_name, kv_cache in kv_caches.items():
spec = self.layer_to_spec[layer_name]
is_mla = isinstance(spec, MLAAttentionSpec)
# Derive block_len from the spec instead of math.prod(shape)
self.block_lens[layer_name] = spec.page_size_bytes // (...)This way "is this layer MLA / key-only?" comes from the spec rather than from len(shape) == 3
Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Signed-off-by: Jun Kang Chow <junkangchow@gmail.com>
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Hi @inkcherry, The connector now uses KVCacheSpec to identify MLA cache layers instead of relying only on tensor shape. Tensor shape/stride is only used for physical offset computation. Verified MiniMax-M3 MXFP8 on 8x MI355X, 1P1D TP4+TP4, MoRIIO READ mode with XGMI. GSM8K 5-shot full run result is ~0.955 exact match. Also verified Qwen3-235B-A22B-FP8 with the same MoRIIO READ mode + XGMI setup to make sure the existing dense K/V path is not regressed. GSM8K 5-shot full run result:
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Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Jun Kang Chow <junkangchow@gmail.com> Co-authored-by: Chun Fang <chun.fang@amd.com> Co-authored-by: TianDi101 <ditian12@amd.com> Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Refactor MoRIIO KV layout offsets and add unit tests
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For visibility, we have two follow-up MoRIIO branches staged on top of this READ-layout fix, from SemiAnalysisAI/InferenceX#1762 but we are not opening them against upstream
After this PR merges, we plan to rebase each branch onto upstream |
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Verified the updated commit with end-to-end lm-eval GSM8K runs using MoRIIO READ mode with the XGMI and RDMA backend on an 8x MI355X intranode 1P1D TP4+TP4 setup. Results:
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Ran MLA model DeepSeek-V2-Chat-0628 Eval: GSM8K full, 25-shot, Results:
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Hi @junkang1991, the pre-commit checks have failed. Please run: uv pip install pre-commit>=4.5.1
pre-commit install
pre-commit run --all-filesThen, commit the changes and push to your branch. For future commits, |
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
…llm-project#46039) Signed-off-by: Jun Kang Chow <junkangchow@gmail.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com> Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Chun Fang <chun.fang@amd.com> Co-authored-by: TianDi101 <ditian12@amd.com> Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com> Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
…llm-project#46039) Signed-off-by: Jun Kang Chow <junkangchow@gmail.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com> Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Chun Fang <chun.fang@amd.com> Co-authored-by: TianDi101 <ditian12@amd.com> Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com> Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
…llm-project#46039) Signed-off-by: Jun Kang Chow <junkangchow@gmail.com> Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: Hongxia Yang <hongxia.yang@amd.com> Co-authored-by: Tan Pin Siang <tanpinsiang@gmail.com> Co-authored-by: vllmellm <vllm.ellm@embeddedllm.com> Co-authored-by: Chun Fang <chun.fang@amd.com> Co-authored-by: TianDi101 <ditian12@amd.com> Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com> Co-authored-by: tjtanaa <tunjian.tan@embeddedllm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Signed-off-by: Qiang Li <qiang.li2@amd.com>
Purpose
Fix MoRIIO READ-mode KV transfer when a model uses mixed per-layer KV cache layouts, observed with MiniMax-M3.
MiniMax-M3 registers multiple KV cache layouts:
MoRIIO previously reused layout assumptions and READ transfer offsets derived from one representative layer. That can read or register the wrong memory region when dense K/V layers and 3D key-only/indexer layers are mixed, causing corrupted decode output in P/D disaggregated serving.
This PR makes MoRIIO READ layout handling per-layer and layout-aware.
Fixes #45885.
Scope
This PR only fixes MoRIIO READ-mode per-layer KV layout handling.
It does not include:
Changes
Validation
Unit / static checks
Test Plan
Tested MiniMax-M3 MXFP8 on an 8x MI355X intranode setup with 1P1D PD disaggregation:
vllm-routerStart vLLM router
docker run --rm --network host vllm/vllm-router:nightly \ vllm-router \ --host 127.0.0.1 \ --port 30000 \ --vllm-pd-disaggregation \ --kv-connector moriio \ --vllm-discovery-address "0.0.0.0:36367"Start prefill instance
Start decode instance
Run GSM8K lm-eval
Test Results
GSM8K 5-shot full run, 1319 examples:
RDMA E2E
Validated MiniMax-M3 BF16 on an 8x MI350X node using MoRIIO READ mode over RDMA P/D:
Results:
This PR is co-authored by
@vllmellm @hongxiayang @junkang1991 @tanpinsiang @chunfangamd @TianDi101 @functionstackx.