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Mike Chandler reposted thisMike Chandler reposted thisASIC / SoC DV Team Available to Deploy Now Looking to accelerate your silicon verification programs with an experienced and scalable DV team? VeriFast Technologies offers a ready-to-deploy ASIC/SoC Design Verification team with deep expertise in: • PCIe Gen4/5/6 • UCIe & CXL • Ethernet MAC/PHY • ARM & RISC-V SoCs • Emulation (Zebu / Veloce) If your team is looking for strong DV expertise and faster execution with Senior Technical Leadership, let’s connect at sales@verifasttech.com. #ASIC #SoC #DesignVerification #UVM #SystemVerilog #PCIe #CXL #UCIe #RiscV #SoC #Semiconductor #VLSI #DV #Emulation #VeriFastTechnologies #India #Vietnam #USA #EU
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Mike Chandler shared thisNeed DV? PCIe Gen5/6, CXL, UCIe, UALink, RISC-V, SoC ...Mike Chandler shared thisASIC / SoC DV Team Available to Deploy Now Looking to accelerate your silicon verification programs with an experienced and scalable DV team? VeriFast Technologies offers a ready-to-deploy ASIC/SoC Design Verification team with deep expertise in: • PCIe Gen4/5/6 • UCIe & CXL • Ethernet MAC/PHY • ARM & RISC-V SoCs • Emulation (Zebu / Veloce) If your team is looking for strong DV expertise and faster execution with Senior Technical Leadership, let’s connect at sales@verifasttech.com. #ASIC #SoC #DesignVerification #UVM #SystemVerilog #PCIe #CXL #UCIe #RiscV #SoC #Semiconductor #VLSI #DV #Emulation #VeriFastTechnologies #India #Vietnam #USA #EU
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Mike Chandler reposted thisMike Chandler reposted thisVeriFast Technologies is seeking Senior Verification Engineers in Ahmedabad/Pune. Candidates should have a minimum of 8+ years of hands-on experience with one or more of the following technologies: - PCIe - UCIe - MAC/PHY Ethernet - USB 4.0 - PMIC - Strong SV, UVM Interested candidates kindly connect with me at 9934158404 or can submit their updated CV's to vkeshav@verifasttech.com. Mike ChandlerRajat GoelNishith ShuklaPranav VyasPalak ShahVenu KeshavSameer SinghNidhi Chauhan
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Mike Chandler reposted thisMike Chandler reposted thisASIC / SoC DV Team Available to Deploy Now Looking to accelerate your silicon verification programs with an experienced and scalable DV team? VeriFast Technologies offers a ready-to-deploy ASIC/SoC Design Verification team with deep expertise in: • PCIe Gen4/5/6 • UCIe & CXL • Ethernet MAC/PHY • ARM & RISC-V SoCs • Emulation (Zebu / Veloce) If your team is looking for strong DV expertise and faster execution with Senior Technical Leadership, let’s connect at sales@verifasttech.com. #ASIC #SoC #DesignVerification #UVM #SystemVerilog #PCIe #CXL #UCIe #RiscV #SoC #Semiconductor #VLSI #DV #Emulation #VeriFastTechnologies #India #Vietnam #USA #EU
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Mike Chandler reposted thisMike Chandler reposted thisMeet VeriQuest - AI-Powered Design Verification Agent Accelerate the verification like never before. Our Agent transforms DV workflows with Faster Debugging. Proposed Fix. Quicker tape-outs. Stop chasing bugs. Start solving them instantly. 👉 Are you interested in quicker tape-outs? Let us connect at sales@verifasttech.com #VeriFast #VeriQuest #AIinDV #ChipDesign #Semiconductor #Automation #FutureOfEngineering #VeriFastTechnologies #India #Vietnam #USA #Europe #UAE
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Mike Chandler reposted thisLarge DV team available for deployment! DV Mgr (20 Years'), DV Leads (14 & 10 Years'), more than 10 supporting engineers. Multicore Processor, SoC, PCIe, UCIe, CXL, UALink, AMBA, I2C, SPI, MIPI, etc. Contact Mr. Dhruv Nagadia: dnagadia@verifasttech.com
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Mike Chandler shared thisLarge DV team available for deployment! DV Mgr (20 Years'), DV Leads (14 & 10 Years'), more than 10 supporting engineers. Multicore Processor, SoC, PCIe, UCIe, CXL, UALink, AMBA, I2C, SPI, MIPI, etc. Contact Mr. Dhruv Nagadia: dnagadia@verifasttech.com
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Mike Chandler reposted thisMike Chandler reposted thisMeet VeriQuest - AI-Powered Design Verification Agent Accelerate the verification like never before. Our Agent transforms DV workflows with Faster Debugging. Proposed Fix. Quicker tape-outs. Stop chasing bugs. Start solving them instantly. 👉 Are you interested in quicker tape-outs? Let us connect at sales@verifasttech.com #VeriFast #VeriQuest #AIinDV #ChipDesign #Semiconductor #Automation #FutureOfEngineering #VeriFastTechnologies #India #Vietnam #USA #Europe #UAE
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Mike Chandler reposted thisMike Chandler reposted thisVeriFast Technologies is hiring Sr DV Engineers in Ahmedabad/Pune with 7+ years of hands-on experience with PCIe,UCIe, MAC/PHY ethernet, USB 4.0, PMIC, and strong SV/UVM. Please connect with me at 9934158404 or drop your updated resume here or to vkeshav@verifasttech.com. Mike ChandlerNishith ShuklaRajat GoelPranav VyasPalak ShahVenu Keshav
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Mike Chandler liked thisMike Chandler liked thisTesla just made the first publicly named senior hire for Terafab, the $55 billion chip fab project it runs jointly with SpaceX and xAI. Wall Street is still discussing whether Musk will propose a legal merger. Terafab suggests the operational one is already built. Gary Jiang joined Tesla in June 2026 as Director, Terafab. He spent 17 years and 9 months at Intel, most recently as Factory Manager at the Ocotillo campus in Chandler, Arizona, where he ran the 18A process technology transfer, tool installation, and ramp toward high-volume manufacturing. Earlier he ran 22nm and 14nm high-volume production. He is the first named senior hire tied to Terafab, and by his own LinkedIn profile is on-site in Austin. Terafab was announced by Musk in Austin on 21 March 2026 as a joint effort between Tesla, SpaceX, and xAI, targeting Intel's 14A process node at a single vertically integrated facility. Intel formally joined as manufacturing partner on 7 April 2026. SpaceX's May S-1 disclosed an initial capex commitment of $55 billion, with total investment across phases running up to $119 billion. Tesla itself will not own the high-volume production facilities. SpaceX will, per Musk. The operational integration is not confined to Terafab. Charles Kuehmann has held VP Materials Engineering roles across Tesla and SpaceX for over a decade. Ashok Elluswamy, VP of AI Software at Tesla, has a role at xAI. Silvio Brugada, Senior Director of Vehicle Software at Tesla, also has a role at xAI. Adding Jiang extends the pattern into semiconductor operations. His reporting line runs into a project owned across three legal entities, capitalised through a SpaceX S-1, and dependent on a fourth company's process technology. The merger discussion assumes a corporate event that has not happened yet. Terafab is the operational version of that event, already running. The first named leader started last week. #Tesla #SpaceX #Semiconductors #Terafab #ChipManufacturing #USA #AIInfrastructure
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Mike Chandler liked thisMike Chandler liked thisOne thing I've noticed recently... Candidates aren't just evaluating the company. They're evaluating how quickly the company makes decisions. I've seen talented professionals lose interest—not because of compensation or role—but because the hiring process stretched for weeks without updates. A fast hiring process doesn't mean compromising on quality. It means respecting a candidate's time. Sometimes, the best employer branding isn't a social media campaign. It's a recruiter who communicates consistently and keeps candidates informed. A simple update can leave a lasting impression. What's your take—has hiring speed become a competitive advantage? #TalentAcquisition #Hiring #CandidateExperience #Recruitment
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Mike Chandler liked thisMike Chandler liked thisWe are hiring.... Sr. Design Verification Engineers, 10+ - Ahmedabad & Pune VeriFast Technologies is expanding. We are hiring Sr. Design Verification Engineers in Ahmedabad with min. 10+ years of design verification experience with PCIe/PCI-E, UCIe, CXL, RISC-V along with strong SV, UVM. Hands on with AXI and AHB/APB with ASIC and/or SoC will be nice to have. Qualifications requirements: • Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or related field. • Hands on experience on C/C++, System Verilog, UVM • Understanding, some of the standard protocol interfaces like PCIe, USB etc. • Minimum of 3-5 years of experience in design verification, with a strong focus on IP and SoC verification. • Proficiency in SystemVerilog and experience with UVM methodology. • Solid understanding of digital design principles and ASIC design flows. • Familiarity with on-chip bus protocols like AXI and AHB Intrested candidates, can share their resumes thru InMail.
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Mike Chandler liked thisMike Chandler liked thisI am looking to hire an experienced RTL Design engineer to work on RISC-V based SoC. Experience range: 6 to 8 years Drop email to vkeshav@verifasttech.com Venu Keshav
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Mike Chandler liked thisChiplets for the win indeed ! Tenstorrent has been an awesome AECP partner from the first hour ! Great technology Great team !Mike Chandler liked this𝗝𝗶𝗺 𝗞𝗲𝗹𝗹𝗲𝗿 𝗷𝘂𝘀𝘁 𝘀𝗮𝗶𝗱 𝗧𝗲𝗻𝘀𝘁𝗼𝗿𝗿𝗲𝗻𝘁 𝘄𝗶𝗹𝗹 "𝗯𝗲𝗮𝘁 𝗖𝗲𝗿𝗲𝗯𝗿𝗮𝘀 𝗼𝗻 𝗲𝘃𝗲𝗿𝘆𝘁𝗵𝗶𝗻𝗴." That is a clear statement from someone who does not trade in empty claims. In a recent interview with EE Times, Keller confirmed he has been meeting with Intel and Qualcomm CEOs, saying he is "hoping to get a big deal" out of one of them. He also said Cerebras going public was helpful, specifically in the context of Tenstorrent positioning to beat them. Whether Tenstorrent gets acquired or goes public itself, the company is in the spotlight now. Jim has a tremendous track record — AMD K8, Apple A4/A5, Tesla's FSD chip. He builds architectures that ship. Tenstorrent is building chiplet-based AI processors designed for disaggregated compute. The approach splits inference and training workloads across multiple smaller dies instead of one massive monolithic chip. That matters for cost, yield, and thermal management in production environments. Keller has been public about the limitations of current GPU-centric infrastructure. His pitch is that chiplets give you flexibility at scale without the packaging constraints that come with wafer-scale designs. Cerebras proved the concept. Tenstorrent is positioning to make it commercially viable. Bloomberg reported in May that Tenstorrent has held early-stage takeover conversations with both Intel and Qualcomm. A partnership or acquisition would give either company a credible alternative architecture to work with. Industry analysts have framed Tenstorrent as the only credible RISC-V AI platform on the market that is not building from scratch. The question is not whether chiplet-based AI accelerators are real. The question is whether Tenstorrent can ship at volume before the hyperscalers lock in their next-generation infrastructure plans. Click here to subscribe to The Hirsch Report: https://lnkd.in/gyzanhxn Source Article: https://lnkd.in/gd8ApZGG #AI #Semiconductors #Tenstorrent #Cerebras #Intel #Qualcomm #Chiplets #HirschReport
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Mike Chandler liked thisMike Chandler liked this🌟 Celebrating Excellence, Commitment & Team Spirit! 🌟 At VeriFast Technologies, we believe that great work deserves to be recognized and celebrated. Today, we took a moment to appreciate the dedication, innovation, and passion our team members bring every day. 🏆 Our Reward & Recognition Celebration was a reminder that every contribution matters whether it’s solving complex challenges, supporting teammates, delivering impactful solutions, or going the extra mile. A big congratulations to all our award winners! Your hard work and commitment continue to inspire us. 👏Jay J., Avnita Pal, Jaymik Dave, Rushang Jani, Akshit Kachhadiya, Het Patel, SATWIK ., Rambhai Nandaniya, Mansi Parmar, Kuntal Wani, Drashti Khatri, Tehsim Shaikh, Aparna Menon,Anupam Mathur, Nupur Joshi, Rajkumar Zalavadia and Maulik Shah We are proud of the culture we are building one that values people, encourages growth, and celebrates achievements together. 🚀 Here’s to more milestones, more innovations, and more reasons to celebrate! 🎉 #EmployeeRecognition #TeamVeriFast #WorkCulture #Appreciation #EmployeeEngagement #GrowthMindset #CelebratingSuccess
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Mike Chandler liked thisMike Chandler liked thistensordyne just announced their chip specs. their trick is to turn every multiply into an add using logarithms, a trick from 1962 that everyone tried and gave up on. here's the breakdown: the idea is simple. log(a×b) = log(a) + log(b). store your numbers as logs and every multiply becomes an add. and a multiplier is expensive: its area grows roughly quadratically with bit width, while an adder grows linearly. do the whole matmul in the log domain and your compute units get tiny! that's basically tensordyne's entire bet. you shrink the multipliers, and spend the freed silicon on memory. but if it's so obvious, how come everyone else abandoned this before? because of addition - once your numbers are logs, adding two of them is no longer an add. it's a nonlinear function that normally needs a lookup table per operation. fine for workloads that are mostly multiplies. terrible for AI, where a matmul is a 50/50 split of multiplies and adds. the adds eat back everything the multiplies saved. tensordyne's says they have a fix for this. they start from the mitchell approximation (log2(1+x) ≈ x), whose error is one-sided and compounds over a long dot product. then they bolt on cheap corrections, just bit shifts, truncations and rounding, that cut the average error by about 100x. multiply in the log domain, convert back, accumulate in linear. no lookup tables, no taylor series. and because the conversion is accurate, you don't retrain or recalibrate the model to run on it. (this is the former recogni. their first chip shipped this math in 7nm for self-driving cars. napier points the same idea at the datacenter.) now the chip details. napier is TSMC 3nm, 138 billion transistors, 300W. 48 logarithmic cores, each a 128x128 systolic array, plus 16 risc-v cores for routing and the decode loop. the claims are 13x the tokens per second and 17x the tokens per watt of a GB300 rack. a tensordyne rack is 288 chips at 300W. an nvidia rack is 72 GPUs at 1,200W. that's the same 86kW of accelerators either way. so 4x of that "13x" is just packing 4x more chips into the same power. the real per-chip win is closer to 3.3x. and the rack has fewer FP4 flops than a GB300, so the throughput isn't coming from compute. it's the extra memory plus a latency-bound operating point where gpus sit underused. it's also all simulation, so don't celebrate yet. the chip just taped out. systems ship in 2027, when the thing to beat is Rubin. curious to hear people's thoughts on this unique approach.
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Since 2007 I have been a volunteer and coach for 8 soccer teams, 3 football teams, 3 baseball teams, and even a mountain biking team. I enjoy taking time out of my busy schedule to coach kids and teach them the value of good sportsmanship, perseverance, and respect.
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Adam Gieras
Libero: The Secure & Reliable FPGA Design Suite EDA Tools for FPGA Engineers Series - Post 3/13 BLUF: If you’re working with Microchip Technology Inc. FPGAs, especially in aerospace, defense, or anything radiation-tolerant, Libero is the tool that keeps your project safe, deterministic, and certifiable. What Makes Libero Stand Out Libero is built around one mission: Reliability and determinism above everything. Microchip’s FPGA families (PolarFire, RT PolarFire, SmartFusion, IGLOO) are known for: ✔ Low power ✔ High security ✔ Excellent radiation performance ✔ Long product lifecycles (think 15+ years) And Libero matches that philosophy - the tool is stable, predictable, and certification-friendly. 💪 Advantages 1. Designed for reliability-critical systems Perfect for aerospace, defense, medical, industrial - anywhere where failure = disaster. 2. Lower power consumption tools Built-in optimizers for PolarFire low-power architecture. 3. Excellent security workflows Secure boot, bitstream protection, crypto accelerators - all well-supported. 4. Stable as a rock No surprise crashes. No drama. Libero is the “calm engineer” of FPGA tools. 5. Long-term support Microchip guarantees availability for decades, not years. 😅 Disadvantages 1. Not the fastest tool on the block Synthesis and P&R can feel… leisurely. 2. Smaller IP ecosystem Compared to Xilinx/Altera, expect fewer “ready-made everything” IPs. 3. STEEP learning curve for first-time users Some workflows feel like they were designed by engineers who really love complexity. 4. Limited device range If you want ultra-high-end DSP or AI acceleration → Xilinx/Altera still dominate. 5. Debug tools not as extensive You’ll miss ILA if you come from Vivado. 😂 Meme Summary Libero: “We don’t crash.” Vivado & Quartus: “Teach us your ways, master.” Libero: “Stability is a lifestyle.” Conclusion If your project cares about security, power efficiency, determinism, or radiation tolerance, Libero is exactly where you should be. It’s the trusted toolchain behind some of the world’s most mission-critical systems. 👉 Working with PolarFire or RT FPGAs? Need help designing, verifying, or building certifiable systems? Finish your FPGA project with us. Let’s talk. Write a direct message!
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Kevin Carlile
Interesting read..... Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may include intermediate interposers that allow higher routing density, enabling an increase in functionality and integration in a single standard or advanced package. This article delves into some of the key chiplet design and integration issues and decisions facing system designers.
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